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this document is a general product description and is subjec t to change without notice. hynix electronics does not assume any responsibility for use of circuits de scribed. no patent licenses are implied. rev 1.0/ july. 2004 1 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 256mb ddr2 sdram hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f
rev 1.0/july. 2004 2 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f revision history rev. history draft date 0.1 initial release dec. 2003 0.2 editorial clean up, changed tras spec. for ddr2 400 jan. 2004 0.3 1) defined idd spec. 2) added speed bins table in ac timming specification may 2004 1.0 transfered functional description, comman d truth table pages and some contents of operating conditions to jul. 2004
3 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f contents 1. description 1.1 device features and ordering information 1.1.1 key feaures 1.1.2 ordering information 1.1.3 ordering frequency 1.2 pin configuration 1.3 pin description 2. maximum dc ratings 2.1 absolute maximum dc ratings 2.2 operating temperature condition 3. ac & dc oper ating conditions 3.1 dc operating conditions 5.1.1 recommended dc operating conditions(sstl_1.8) 5.1.2 odt dc electri cal characteristics 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions 3.2.4 differential input ac logic level 3.2.5 differential ac output parameters 3.3 output buffer levels 3.3.1 output ac test conditions 3.3.2 output dc current drive 3.3.3 ocd default chracteristics 3.4 idd specifications & measurement conditions 3.5 input/output capacitance 4 . ac timing specifications 5. package dimensions
rev 1.0/july. 2004 4 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 1.1 device features & ordering information 1.1.1 key features ? vdd=1.8v ? vddq=1.8v +/- 0.1v ? all inputs and outputs are compatible with sstl_18 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous-data transaction aligne d to bidirectional da ta strobe (dqs, dqs ) ? differential data strobe (dqs, dqs ) ? data outputs on dqs, dqs edges when read (edged dq) ? data inputs on dqs centers when write(centered dq) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm mask write data-in at the both risi ng and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and da ta masks latched on the rising edges of the clock ? programmable cas latency 3, 4, 5 and 6 supported ? programmable additive latency 0, 1, 2, 3, 4 and 5 supported ? programmable burst length 4/8 with both nibble sequential and interleave mode ? internal four bank operatio ns with single pulsed ras ? auto refresh and self refresh supported ? tras lockout supported ? 8k refresh cycles /64ms ? jedec standard 60ball fbga(x4/x8) & 84ball fbga(x16) ? full strength driver option controlled by emrs ? on die termination supported ? off chip driver impedance adjustment supported ? read data strobe suupported (x8 only) ? self-refresh high temperature entry ordering information part no. configuration package hy5ps56421(l)f-x* 64mx4 60ball fbga hy5ps56821(l)f-x* 32mx8 hy5ps561621(l)f-x* 16mx16 84ball fbga operating frequency grade tck(ns) cl trcd trp unit -e3 5333 clk -e4 5444 clk -c4 3.75 4 4 4 clk -c5 3.75 5 5 5 clk -y5 3555 clk -y6 3666 clk note: -x* is the speed bin, refer to the operation frequency table for complete part no. 1. description
5 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 1.2 pin configuration & address table 64mx4 ddr2 pin configuration 3 vss dm vddq dq3 vss we ba1 a1 a5 a9 nc 2 nc vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 1 vdd nc vddq nc vddl nc vss vdd a b c d e f g h j k l 7 vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc 8 dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 9 vddq nc vddq nc vdd odt vdd vss row and column address table items 64mx4 # of bank 4 bank address ba0, ba1 auto precharge flag a10/ap row address a0 - a12 column address a0-a9, a11 page size 1 kb
rev 1.0/july. 2004 6 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 32mx8 ddr2 pin configuration 3 vss dm, rdqs vddq dq3 vss we ba1 a1 a5 a9 nc 2 nu, rdqs vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 1 vdd dq6 vddq dq4 vddl nc vss vdd a b c d e f g h j k l 7 vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc 8 dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 9 vddq dq7 vddq dq5 vdd odt vdd vss row and column address table items 32mx8 # of bank 4 bank address ba0, ba1 auto precharge flag a10/ap row address a0 - a12 column address a0-a9 page size 1 kb
rev 1.0/july. 2004 7 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 16mx16 ddr2 pin configuration 3 vss udm vddq dq11 vss we ba1 a1 a5 a9 nc 2 nc vssq dq9 vssq vref cke ba0 a10 a3 a7 a12 1 vdd dq14 vddq dq12 vddl nc vss vdd a b c d j k l m n p r 7 vssq udqs vddq dq10 vssdl ras cas a2 a6 a11 nc 8 udqs vssq dq8 vssq ck ck cs a0 a4 a8 nc 9 vddq dq15 vddq dq13 vdd odt vdd vss vss ldm vddq dq3 nc vssq dq1 vssq vdd dq6 vddq dq4 e f g h vssq ldqs vddq dq2 ldqs vssq dq0 vssq vddq dq7 vddq dq5 row and column address table items 16mx16 # of bank 4 bank address ba0, ba1 auto precharge flag a10/ap row address a0 - a12 column address a0-a8 page size 1 kb
rev 1.0/july. 2004 8 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 1.3 pin description pin type description ck, ck input clock: ck and ck are differential clock inputs. all addr ess and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is refer- enced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high ac tivates, and cke low deactivates in ternal clock sign als, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all bank s idle), or active power down (row active in any bank). cke is synchronous for power down entry and ex it, and for self refres h entry. cke is asyn- chronous for self refresh exit. after v ref has become stable during the power on and initial- ization sequence, it must be maintained for proper operation of the cke receiver. for proper self- refresh entry and exit, v ref must be maintained to this inpu t. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down. input buffers, excludin g cke are disabled during self refresh. cs input chip select : all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. odt input on die termination control : odt(registered high ) enables on die termin ation resistance inter- nal to the ddr2 sdram. when enabled, odt is only applied to dq, dqs, dqs , rdqs, rdqs , and dm signal for x4,x8 configurations. for x 16 configuration odt is applied to each dq, udqs/udqs .ldqs/ldqs , udm and ldm signal. the odt pin will be ignored if the extended mode register(emrs(1)) is programmed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm (ldm, udm) input input data mask : dm is an input mask signal fo r write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs, although dm pins are input only, the dm loading matches the dq and dqs load- ing. for x8 device, the function of dm or rdqs/ rdqs is enabled by emrs command. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied(for 256mb and 512mb, ba2 is not applied). bank address also deter- mines if the mode register or extended mode regi ster is to be accessed during a mrs or emrs cycle. a0 -a15 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled du ring a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0-ba2. the address inputs also provide the op code during mode register set commands. dq input/output data input / output : bi-directional data bus dqs, (dqs) (udqs),(udqs ) (ldqs),(ldqs ) (rdqs),(rdqs ) input/output data strobe : output with read data, input with write data. edge aligne d with read data, cen- tered in write data. for the x16, ldqs correspond to the data on dq0~dq7; udqs corresponds to the data on dq8~dq15. for the x8, an rdqs option using dm pin can be enabled via the emrs(1) to simplify read timing. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with optional complementary signals dqs, ldqs,udqs and rdqs to provide differential pair signaling to the sy stem during both reads and wirtes. an emrs(1) control bit enables or disables all complementary data strobe signals. in this data sheet, "differential dqs signals" refe rs to any of the following with a10 = 0 of emrs(1) x4 dqs/dqs x8 dqs/dqs if emrs(1)[a11] = 0 x8 dqs/dqs , rdqs/rdqs , if emrs(1)[a11] = 1 x16 ldqs/ldqs and udqs/udqs "single-ended dqs signals" refers to any of the following with a10 = 1 of emrs(1) x4 dqs x8 dqs if emrs(1)[a11] = 0 x8 dqs, rdqs, if emrs(1)[a11] = 1 x16 ldqs and udqs
rev 1.0/july. 2004 9 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f -continue- pin type description nc no connect : no internal electrical connection is present. v ddq supply dq ground vssq supply dq power supply : 1.8v +/- 0.1v v ddl supply dll power supply : 1.8v +/- 0.1v v ssdl supply dll ground vdd supply power supply : 1.8v +/- 0.1v v ss supply ground v ref supply reference voltage for inputs for sstl interface.
rev 1.0/july. 2004 10 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 2.1 absolute maximum dc ratings 2.2 operating temperature condition symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in , v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 1. . stresses greater than those listed under ?absolute maximum ratings? may cause perma nent damage to the device. this is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operati onal sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. storage temperature is the case surface temperature on th e denter/top side of the dram. for the measurement conditions. please refer to jesd51-2 standard. symbol parameter rating units notes toper operating temperature 0 to 85 c 1,2 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 2. the operatin temperature range are the temperature where all dra m specification will be supported. outside of this temperatur e rang, even it is still within the limit of stress condition, some deviation on porti on of operation specification may be requir ed. during operation, the dram case temperature must be maintained between 0 ~ 85 c under all other specification parameters. however, in some applications, it is desirable to operate the dram up to 95 c case temperature. therefore 2 spec options may exist. 1) supporting 0 - 85 c with full jedec ac & dc specifications. this is the minimum requirements for all oprating temperature options. 2) supporting 0 - 85 c and being able to extend to 95 c with doubling auto-refresh commands in frequency to a 32 ms period(trfi=3.9us). note; currently the periodic self-refresh interval is hard coded within the dram to a specificic value. there is a migration plan to support higher temperature self-ref resh entry via the control of emrs(2) bit a7. however, since self-refresh control function is a migrat ed process. for our ddr2 module user, it is imperative to check spd byte 49 bit 0 to ensure the dram parts support higer than 85 c case temperature self-refresh entry. 1) if spd byte 49 bit 0 is a ?0? means dram does not support self-refresh at higher than 85 c, then system have to ensure the dram is at or below 85 c g case temperature before initiating self-refresh operation. 2) if spd byte 49 bit 0 is a ?1? means dram supports self-refresh at higher than 85 c g case temperature, then system can use register bit a7 at emrs(2) control dram to operate at pr oper self-refresh rate for higher temperature. please also refer to emrs(2) register definition section and ddr2 dimm spd definition for details. 2. maximum dc ratings
rev 1.0/july. 2004 11 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 3.1 dc operating conditions 3.1.1 recommended dc operating conditions (sstl_1.8) 3.1.2 odt dc electrical characteristics note 1: test condition for rtt measurements note 2: optional for ddr2-400/533/667 measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately , then measure current i(v ih (ac)) and i( v il (ac)) respectively. v ih (ac), v il (ac), and vddq values defined in sstl_18 measurement definition for vm : measurement voltage at test pin(mid point) with no load. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v vddl supply voltage for dll 1.7 1.8 1.9 v 4 vddq supply voltage for output 1.7 1.8 1.9 v 4 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 1, 2 vtt termination voltage v ref -0.04 v ref v ref +0.04 v 3 there is no specific device vdd supply voltage requirement fo r sstl-1.8 compliance. however under all conditions vddq must be less than or equal to vdd. 1. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq tracks with vdd, vddl tracks with vdd. ac para meters are measured with vdd, vddq and vdddl tied together parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a 6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6, a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6, a2)=1,1; 550 ohm rtt2(eff) 40 50 60 ohm 1,2 deviation of v m with respect to vddq/2 delta vm -6 +6 % 1 delta vm = 2 x vm vddq x 100% - 1 3. ac & dc operating conditons rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) )
rev 1.0/july. 2004 12 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 3.2.1 input dc logic leve l 3.2.2 input ac logic level 3.2.3 ac input test conditions notes: 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching fr om vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter min. max. units notes v ih (ac) ac input logic high v ref + 0.250 - v v il (ac) ac input logic low -v ref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr 3.2 dc & ac logic input levels < figure : ac input test signal waveform>
rev 1.0/july. 2004 13 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 3.2.4 differential input ac logic level 1. v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id(dc ) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih(dc) - v il(dc) . notes: 1. v id(ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih(ac) - v il(ac) . 2. the typical value of v ix(ac) is expected to be about 0.5 * vddq of the transmitting device and v ix(ac) is expected to track variations in vddq . v ix(ac) indicates the voltage at which diff erential input signals must cross. 3.2.5 differential ac output parameters notes: 1. the typical value of v ox(ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox(ac ) is expected to track variations in vddq . v ox(ac) indicates the voltage at whitch differential output signals must cross. symbol parameter min. max. units notes v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units notes v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev 1.0/july. 2004 14 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 3.3 output buffer characteristics 3.3.1 output ac t est conditions 3.3.2 output dc current drive 3.3.3 ocd defalut characteristics note 1: absolute sp ecifications (0c t case +tbdc; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v) note 2: impedance measurement condition for output source dc current: vddq = 1.7v; vout = 1420mv; (vout-vddq)/ioh must be less t han 23.4 ohms for values of vout between vddq and vddq-280mv. impedance measurement condition for output sink dc current: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ohms for va lues of vout between 0v and 280mv. note 3: mismatch is absolute value between pull-up an d pull-dn, both are measured at same temperature and voltage. note 4: slew rate measured from vil(ac) to vih(ac). note 5: the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. note 6: this represents the step size when the ocd is near 18 ohms at nominal conditions across all process corners/variations and represents only the dram uncer tainty. a 0 ohm value(no calibration) can only be achieved if the ocd impedance is 18 ohms +/- 0.75 ohms under nominal conditions. symbol parameter sstl_18 class ii units notes v otr output timing measurement reference level 0.5 * v ddq v1 1. the vddq of the device under test is referenced. symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 a nd 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shi fting the desired driver operating point (see se ction 3.3) along a 21 ohm load line to define a convenient driver current for measurement. description parameter min nom max unit notes output impedance 12.6 18 23.4 ohms 1,2 output impedance step size for ocd cali- bration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 - 5 v/ns 1,4,5,6,7,8
rev 1.0/july. 2004 15 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f output slew rate load: note 7: dram output slew rate specificat ion applies to 400mt/s & 533mt/s speed bins. note 8: timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. vtt 25 ohms output (vout) reference point
rev 1.0/july. 2004 16 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f idd specifications(max) symbol ddr2 400 ddr2 533 ddr2 667 units x4 x8 x16 x4 x8 x16 x4 x8 x16 idd0 100 105 110 110 115 120 120 125 130 ma idd1 110 115 120 120 125 130 130 135 140 ma idd2p 555555555 ma idd2q 40 40 40 45 45 45 50 50 50 ma idd2n 50 50 50 55 55 55 60 60 60 ma idd3p f 30 30 30 30 30 30 30 30 30 ma s 20 20 20 20 20 20 20 20 20 ma idd3n 65 70 75 75 80 85 80 85 95 ma idd4w 165 175 185 190 210 220 230 250 260 ma idd4r 160 170 180 185 205 215 225 245 255 ma idd5 150 150 150 160 160 160 170 170 170 ma idd6 nor- mal 444444444 ma low power 222222222 ma idd7 230 250 270 240 260 280 250 270 290 ma 3.4 idd specifications & test conditions
17 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f idd test conditions (idd values are for full operating range of voltage and temperature, notes 1-5) note: 1. idd specifications are tested afte r the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are s pecified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be met with all combina- tions of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low ever y other data transfer (once per clock) for dq signals not incl uding masks or strobes . symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras min(idd) ; cke is high, cs is high between valid commands;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are sw itching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other contro l and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addre ss bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pat- tern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev 1.0/july. 2004 18 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f for purposes of idd testing, the following parameters are to be utilized detailed idd7 the detailed timings are shown below for i dd7. changes will be required if timing parame ter changes are made to the specificati on. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8/ x16 -ddr2-400 4/4/4: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d d -ddr2-400 3/3/3: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d -ddr2-533 5/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -ddr2-533 4/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d timing patterns for 8 bank devices x4/8 -ddr2-400 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 a4 ra4 a5 ra5 a6 ra6 a7 ra7 -ddr2-533 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d timing patterns for 8 bank devices x16 -ddr2-400 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -ddr2-533 all bins: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 d a6 ra6 d a7 ra7 d d d ddr2-667 ddr2-533 ddr2-400 parameter 5-5-5 6-6-6 4-4-4 5-5-5 3-3-3 4-4-4 units cl(idd) 564534tck t rcd(idd) 15 18 15 18.75 15 20 ns t rc(idd) 60 63 60 63.75 55 65 ns t rrd(idd)-x4/x8 7.5 7.5 7.5 7.5 7.5 7.5 ns t rrd(idd)-x16 9910 10 10 10 ns t ck(idd) 3 3 3.75 3.75 5 5 ns t rasmin(idd) 45 45 45 45 40 45 ns t rasmax(idd) 70000 70000 70000 70000 70000 70000 ns t rp(idd) 15 18 15 18.75 15 20 ns t rfc(idd)-256mb 75 75 75 75 75 75 ns t rfc(idd)-512mb 105 105 105 105 105 105 ns t rfc(idd)-1gb 127.5 127.5 127.5 127.5 127.5 127.5 ns t rfc(idd)-2gb 197.5 197.5 197.5 197.5 197.5 197.5 ns
rev 1.0/july. 2004 19 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 3.5. input/output capacitance 4. electrical characteristics & ac timing specification ( 0 t case 95; v ddq = 1.8 v +/- 0.1v; v dd = 1.8v +/- 0.1v) refresh parameters by device density ddr2 sdram speed bins and trcd, trp and trc for corresponding bin note 1: 8 bank device precharge all allowance : trp for a precharge all command for and 8 bank device will equal to trp+1*tck, where trp are the values for a single bank prechrarge, which are shown in the above table. parameter symbol ddr2 400 ddr2 533 ddr2 667 ddr2 800 units min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 pf parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 t case 95 7.8 7.8 7.8 7.8 7.8 ns 85 t case 95 3.9 3.9 3.9 3.9 3.9 ns speed ddr2-667 ddr2-533 ddr2-533 ddr2-533 ddr2-400 ddr2-400 units bin(cl-trcd-trp) 4-4-4 3-3-3 4-4-4 5-5-5 3-3-3 4-4-4 parameter min min min min min min cas latency 434534tck trcd 12 11.25 15 18.75 15 20 ns trpnote1 12 11.25 15 18.75 15 20 ns tras 45 45 45 45 40 40 ns trc 57 56.25 60 63.75 55 65 ns
rev 1.0/july. 2004 20 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f timing parameters by speed grade parameter symbol ddr2-400 ddr2-533 unit note min max min max dq output access time from ck/ck tac -600 +600 -500 +500 ps dqs output access time from ck/ck tdqsck -500 +500 -450 +450 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 5000 8000 3750 8000 ps 15 dq and dm input setup time tds 150 - 100 - ps 6,7,8,20 dq and dm input hold time tdh 275 - 225 - ps 6,7,8,21 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps 18 dqs low-impedance time from ck/ck tlz (dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ck tlz (dq) 2*tac min tac max 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq - 350 -300 ps 13 dq hold skew factor tqhs - 450 -400 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 write preamble twpre 0.35 - 0.35 - tck address and control input setup time tis 350 - 250 - ps 5,7,9,23 address and control input hold time tih 475 - 375 - ps 5,7,9,23 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to active command period for 1kb page size products trrd 7.5 -7.5 - ns 4 active to active command period for 2kb page size products trrd 10 -10 - ns 4 four active window for 1kb page size products tfaw 37.5 - 37.5 - ns
rev 1.0/july. 2004 21 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f parameter symbol ddr2-400 ddr2-533 unit note min max min max four active window for 2kb page size products tfaw 50 -50 - cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp* - wr+trp* - tck 14 internal write to read command delay twtr 10 -7.5 - ns 24 internal read to precharge command delay trtp 7.5 7.5 ns 3 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max)+ 1 tac(min) tac(max) +1 ns 16 odt turn-on(power-down mode) t aonpd tac(min)+ 2 2tck+tac( max) +1 tac(min)+ 2 2tck+tac (max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 tac(min) tac(max) + 0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min)+ 2 2.5tck+ta c(max)+1 tac(min)+ 2 2.5tck+ta c(max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+ti h tis+tck+ti h ns 15 -continued
rev 1.0/july. 2004 22 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f * : tras(min) , trc(min) specification for ddr2-400 4-4-4 is 45ns, 60ns respectively. parameter symbol ddr2-667 unit note min max dq output access time from ck/ck tac -450 +450 ps dqs output access time from ck/ck tdqsck -400 +400 ps ck high-level width tch 0.45 0.55 tck ck low-level width tcl 0.45 0.55 tck ck half period thp min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 3000 8000 ps 15 dq and dm input setup time tds 50 - ps 6,7,8,20 dq and dm input hold time tdh 175 - ps 6,7,8,21 control & address input pulse width for each input tipw 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - tck data-out high-impedance time from ck/ck thz - tac max ps 18 dqs low-impedance time from ck/ck tlz (dqs) tac min tac max ps 18 dq low-impedance time from ck/ck tlz (dq) 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq - 240 ps 13 dq hold skew factor tqhs - 340 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 - tck dqs input low pulse width tdqsl 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - tck mode register set command cycle time tmrd 2 - tck write postamble twpst 0.4 0.6 tck 10 write preamble twpre 0.35 - tck address and control input setup time tis 150 - ps 5,7,9,22 address and control input hold time tih 275 - ps 5,7,9,23 read preamble trpre 0.9 1.1 tck 19 read postamble trpst 0.4 0.6 tck 19 activate to precharge command tras 45 70000 ns 3 active to active command period for 1kb page size products trrd 7.5 - ns 4 active to active command period for 2kb page size products trrd 10 - ns 4 four active window fo r 1kb page size products tfaw 37.5 - ns cas to cas command delay tccd 2 tck
rev 1.0/july. 2004 23 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f -continued parameter symbol ddr2-667 unit note min max four active window for 2kb page size products tfaw 50 - ns cas to cas command delay tccd 2 tck write recovery time twr 15 - ns auto precharge write recovery + precharge time tdal wr+trp - tck 14 internal write to read command delay twtr 7.5 - ns internal read to precharge command delay trtp 7.5 ns 3 exit self refresh to a non-read command txsnr trfc + 10 ns exit self refresh to a read command txsrd 200 - tck exit precharge power down to any non-read command txp 2 - tck exit active power down to read command txard 2 tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 tck odt turn-on delay t aond 22tck odt turn-on t aon tac(min) tac(max)+0.7 ns 6,16 odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+tac(ma x) +1 ns odt turn-off delay t aofd 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 ns 17 odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck+tac( max)+1 ns odt to power down entry latency tanpd 3 tck odt power down exit latency taxpd 8 tck ocd drive mode output delay toit 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih ns 15
rev 1.0/july. 2004 24 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f general notes, which may ap ply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling a nd rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b. input slew rate for single ended signals is measur ed from dc-level to ac-level: from vref - 125 mv to vref + 250 mv for rising edges and from vref + 125 mv and vref - 250 mv for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv (250mv to -5 00 mv for falling egdes). c. vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 2. ddr2 sdram ac timing reference load the following figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise repr esentation of the typical syst em environment nor a depic- tion of the actual load pr esented by a production tester. system de signers will use ibis or other simulation tools to correlate the timing referenc e load to a system environment. manu facturers will correlate to their pro- duction test conditions (generally a coaxial transmi ssion line terminated at the tester electronics). the output timing reference voltage level for single en ded signals is the crosspoint with vtt. the output tim- ing reference voltage level for different ial signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs) signal. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as shown below. 4. differential data strobe ddr2 sdram pin timings are specified for either singl e ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing ad vantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measur ed is mode depe ndent. in single vddq dut dq dqs dqs rdqs rdqs output v tt = v ddq /2 25 ? timing reference point ac timing reference load vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 ? test point slew rate test load
rev 1.0/july. 2004 25 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f vref. in differential mode, these timing relationships ar e measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guarant eed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resistor to insure proper operation. 5. ac timings are for linear signal transitions. see system derating for other signal transitions. 6. these parameters guarantee device behavior, but t hey are not necessarily test ed on each device. they may be guaranteed by device design or tester correlation. 7. all voltages referenced to vss. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal refer- ence/supply voltage levels, but the rela ted specifications and device operat ion are guaranteed for the full volt- age range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure -- data input (write) timing dmin dmin dmin d d d dqs v ih (ac) v il (ac) v ih (ac) v il (ac) v ih (dc) v il (dc) v ih (dc) v il (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure -- data output (read) timing q qq
rev 1.0/july. 2004 26 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f specific notes for de dicated ac parameters 1. user can choose which active po wer down exit timing to use via mr s(bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. al = additive latency 3. this is a minimum requirement. minimum read to pr echarge timing is al + bl/2 providing the trtp and tras(min) have been satisfied. 4. a minimum of two clocks (2 * tck) is required irrespective of operating frequency 5. timings are guaranteed with command/address input slew rate of 1.0 v/ns. see system derating for other slew rate values. 6. timings are guaranteed with data, mask, and (dqs/rdqs in singled ended mode) input slew rate of 1.0 v/ns. see system derating for other slew rate values. 7. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns . timings are guaranteed for dqs sig- nals with a differential slew rate of 2. 0 v/ns in differential strobe mode and a slew rate of 1v/ns in single ended mode. see system derating for other slew rate values. 8. tds and tdh derating 1) for all input signals the total tds(setup time) and tdh(hold time) required is calculated by adding the datasheet value to t he derating value listed in table x. setup(tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vih(ac)min. setup(tds) nominal slew ra te for a falling signal is defined as the slew rate between the last crossing of vref( dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nom inal slew rate line between shaded ? vref(dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the act ual signal is later than the nominal slew rate line anywhere bet ween shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for deratin g value(see fig b.) hold(tdh) nominal slew rate for a rising si gnal is defined as the slew rate rate bet ween the last crossing of vil(dc) max and t he first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate bet ween the last crossing of vih(dc) min and the first crossing of vref(dc). if the actual signal is earlier than the nom inal slew rate line anywhere between shaded ?dc to vref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value(see fig d.) although for slow slew rates the total setup time might be negativ e(i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to co mplete the transition and reach vih/il(ac). for slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation. these values are typically not subj ect to production test. they are veri fied by design and characterization. td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h 2.01254512545+125+45------------ 1.583218321+83+219533---------- 1.000000012122424 -------- 0.9---11-14-11-141-213102522------ 0.8-----25-31-13-19-1-71152317---- 0.7 - - - - -43 -54 -31 -42 -42 -19 -7 -8 5 -6 17 6 - - 0.6 - - - - -67 -83 - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11 0.5-----110-125-----74-89-62-77-50-65-38-53 0.4-----175-188-------127-140-115-128-103-116 dq slew rate v/ns dqs, dqs differential slew rate tds, tdh derating values(all units in 'ps', note 1 applies to entire table) 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 0.8 v/ns
27 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f fig. a illustration of nomi nal slew rate for tis,tds ck,dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (ac)max setup slew rate falling signal = delta tf v ih (ac)min-v ref (dc) setup slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh ck, dqs
28 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f fig. -b illustration of tangent line for tis,tds ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region tangent line tangent line t is , t ds ck, dqs nomial line nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] setup slew rate rising signal = tangent line[v ref (dc)-v il (ac)max] setup slew rate falling signal = delta tf t ih , t dh t is , t ds t ih , t dh
29 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f fig. -c illustration of nom inal line for tih, tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tr nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (dc)max hold slew rate rising signal = delta tr v ih (dc)min - v ref (dc) hold slew rate falling signal = delta tf dc to v ref region delta tf ck, dqs t ih , t dh t is , t ds t ih , t dh
30 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f fig. -d illustration of ta ngent line for tih , tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf tangent line tangent line t is , t ds ck, dqs nominal line dc to v ref region nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] hold slew rate falling signal = delta tf tangent line[v ref (dc)-v il (ac)max] hold slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh
31 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 9. tis and tih (input setup and hold) derating 1) for all input signals the total tis(setup time) and tih(hold) time) required is calculated by adding the datasheet value to the derating value listed in above table. setup(tis) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup(tis) nomina l slew rate for a falling si gnal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate for line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see fig b.) hold(tih) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref (dc). hold(tih) nominal slew rate fo r a falling signal is defined as the slew rate between the last crossing of v ref (dc). if the actual signal signal is always later than the nominal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value(see fig.c) if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value(see fig d.) tis tih tis tih tis tih uni ts notes 4.0 +187 +94 t bd t bd t bd t bd p s 1 3.5 +179 +89 t bd t bd t bd t bd p s 1 3.0 +167 +83 t bd t bd t bd t bd p s 1 2.5 +150 +75 t bd t bd t bd t bd p s 1 2.0 +125 +45 t bd t bd t bd t bd p s 1 1.5 +83 +21 tbd tbd tbd tbd ps 1 1.0 +0 0 tbd tbd tbd tbd ps 1 0.9 -11 -14 tbd tbd tbd tbd ps 1 0.8 -25 -31 tbd tbd tbd tbd ps 1 0.7 -43 -54 tbd tbd tbd tbd ps 1 0.6 -67 -83 tbd tbd tbd tbd ps 1 0.5 -100 -125 tbd tbd tbd tbd ps 1 0.4 -150 -188 tbd tbd tbd tbd ps 1 0.3 -223 -292 tbd tbd tbd tbd ps 1 0.25 -250 -375 tbd tbd tbd tbd ps 1 0.2 -500 -500 tbd tbd tbd tbd ps 1 0.15 -750 -708 tbd tbd tbd tbd ps 1 0.1 -1250 -1125 tbd tbd tbd tbd ps 1 tis, tih derating values command / address slew rate(v/ns) 2.0 v/ns ck, ck differential slew rate 1.5 v/ns 1.0 v/ns
32 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f although for slow rates the total se tup time might be negative(i.e. a vali d input signal will not have reached v ih/il (ac) at the time of the rising clo ck transition) a valid input signal is still required to comp lete the transition and reach v ih/il (ac). for slew rates in between the values listed in table, t he derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by design and characterization. 10. the maximum limit for this parame ter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnarou nd) will degrade accordingly. 11. min ( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time as pro- vided to the device (i.e. this value can be greater than the minimum specification lim its for t cl and t ch). for example, t cl and t ch are = 50% of the period, less the half period jitter ( t jit(hp )) of the clock source, and less the half period jitter due to crosstalk ( t jit(crosstalk)) into the clock traces. 12. t qh = t hp ? t qhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low ( tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output patter n effects, and p-channel to n-channel variation of the output drivers as well as output sl ew rate mismatch between dqs/ dqs and associated dq in any given cycle. 14. t dal = (nwr) + ( trp/tck): for each of the terms above, if not already an integer, round to the nex t highest integer. tck refers to the application clock period. nwr refers to the t wr parameter stored in the mrs. example: for ddr533 at t ck = 3.75 ns with t wr pr ogrammed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks =4 +(4) clocks=8clocks. 15. the clock frequency is allowed to change during self?refresh mode or precharge power-down mode. in case of clock frequency change during precharge power- down, a specific procedure is required as described in section 2.9. 16. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 17. odt turn off time min is when the de vice starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. 18. thz and tlz transitions occur in the same access time as valid data transitions. thesed parameters are referenced to a specific voltage le vel which specifies when the device ou tput is no longer driving(thz), or begins driving (tlz). below figure shows a method to calculate the point when device is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different voltages. the actual voltage measure- ment points are not critical as long as the calculation is consistenet.
33 rev 1.0 / july. 2004 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f 19. trpst end point and trpre begin point are not refer enced to a specific voltage level but specify when the device output is no longer driving (trpst), or be gins driving (trpre). below figure shows a method to calculate these points when the device is no longer dr iving (trpst), or begins driving (trpre). below figure shows a method to calculate these points when the devic e is no longer driving (trpst), or begins driving (trpre) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. 20. input waveform timing with differential data strobe enabled mr[bit10] =0, is referenced from the input sig- nal crossing at the v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 21. input waveform timing with differential data strobe enabled mr[bit10]=0, is referenced from the input sig- nal crossing at the v ih (dc) level to the differential data strobe crosspoint for a rising signal and v il (dc) to the differential data strobe crossp oint for a falling signal app lied to the devic e under test. 22. input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal app lied to the devic e under test. 23. input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal app lied to the devic e under test. thz , trpst end point = 2*t1-t2 tlz , trpre begin point = 2*t1-t2 voh + xmv voh + 2xmv vol + 1xmv vol + 2xmv thz trpst end point vtt + 2xmv vtt + xmv vtt -xmv vtt - 2xmv thz trpre begin point dqs v ddq v ih(ac) min v ih(dc) min tdh tds dqs v ref (dc) v ss v il(dc) max v il(ac) max tdh tds differential input waveform timing
rev 1.0 / july. 2004 34 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f package dimension(x4,x8) 60ball fine pitch ball grid array outline a1 ball mar k 14.00 +/- 0.10 12.00 +/- 0.10 0.8 x 10 = 8.0 a b c d e f g h j k l 1 2 3 7 8 9 0.34 +/- 0.05 1.20 max. 0.80 0.80 0.80 x 8 = 6.40 a1 ball mark 60 - 0.50 note: all dimension units are millimeters. 5. package dimensions
rev 1.0/july. 2004 35 hy5ps56421(l)f hy5ps56821(l)f hy5ps561621(l)f package dimension(x16) 84ball fine pitch ball grid array outline a1 ball mark 14.00 +/- 0.10 12.00 +/- 0.10 0.8 x 14 = 11.2 a b c d e f g h j k l m n p r 1 2 3 7 8 9 0.34 +/- 0.05 1.20 max. 0.80 0.80 0.80 x 8 = 6.40 a1 ball mark 84 - 0.50 note: all dimension units are millimeters.

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